Did you try the measurement with signaltap Also, it's important to find warnings related to your design files. You need to open the little arrow to the left of that warning so we can see if the GPIO pins you are targeting are part of the list. You can fire it up right from Quartus and its GUI is pretty straight forward, giving you nice drop-downs for signals & pins etc. From the picture you posted one cannot tell which pins are stuck at VCC/GND.
See PinPlanner manual for more information on how to do pin assignments. Most likely you have this problem because you are missing a connection for a signal, or you did not specify pin assignments. Warning (10230): Verilog HDL assignment warning at statemachine.v(15): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at statemachine. DC Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC. If you have that clock_enable stuck, everything that is driven by the clock that signal is gating can be pretty much optimized away. Limits not valid when pin 12 (instead of pin 11) is used.
If synthesis tool determines that a signal from pin A is always 1'b1, then it can optimize your module away and just drive 1'b0 to the pin B.įrom your description, it seems like data_in is an input to FPGA and clock_enable is some signal that gates the clock (i.e. Now let me start with the reasons: I tried to synthesize your instruction memory, it synthesizes, but the Quartus software assumes the memory is filled with 0's and it gives the following warnings (as expected): Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin 'readinstruction 0' is stuck. For example, let's say your module is getting signal from pin A, inverts it and outputs to pin B. Signals can either get stuck at GND (ground), meaning that they are always low (has a value of 1'b0) or they may stuck at VCC (positive supply voltage) when a signal is constantly asserted high (has a value of 1'b1).īecause the signal is constant, synthesis tools is able to perform certain optimizations that could result in reduced logic up to the point when the whole design is optimized away.
FPGA():Output pins are stuck at VCC or GND. You get "Stuck at GND" messages when synthesis tool determines that a particular signal is constant and is never changing. Warning (13024): Output pins are stuck at VCC or GNDWarning (13410): Pin OUTPUTA is stuck at GNDWarning (13410): Pin OUTPUTB i.